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《开源精简指令集处理器RISC-V 》( Open Source CPU RISC-V)[2016-12更新HiFive1 Arduino 兼容开发板][压缩包]

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  • 摘要:
    发行时间2014年
    语言英文
  • 时间: 2015/09/18 23:11:29 发布 | 2017/01/25 18:16:26 更新
  • 分类: 软件  编程开发 

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中文名开源精简指令集处理器RISC-V
英文名 Open Source CPU RISC-V
资源格式压缩包
版本[2016-12更新HiFive1 Arduino 兼容开发板]
发行时间2014年
地区美国
语言英文
简介

IPB Image

直指移动芯片市场,开源的处理器指令集架构发布

IoT(Internet of things,物联网)做为下一代的产业应用,欲藉着在现有的设备中加入微型电脑,将所有东西连上网络来创造新的应用。然而,现行的微型电脑价格依然过高,拖慢 IoT 的发展。其中,在整个微型电脑架构中,最贵的非 CPU 莫属了。

  现在的 IoT 市场,大多考虑采用 ARM 架构的 CPU。虽然相较于其他的处理器平台,ARM 的授权相对灵活,但对 IoT 厂商来说价格仍偏高,使得移动 CPU 的成本价格迟迟降不下来。因此,现行市场急需低成本且稳定的新架构。于是,RISC-V,做为开源的新架构, 跃上舞台。

  在 CPU 中,指令集架构(Instruction Set Architecture,ISA),扮演着重要的角色,ISA 是电脑的基础,整个系统皆顺其而生。此外,ISA 会影响操作系统的种类以及软件的支持程度,因此,每个 ISA 皆有各自的生态。那么市场上常见的 ISA 有哪些呢?

  现行市场主流的指令集架构,能见度最高的就属 X86 和 ARM,X86 由 Intel 主导,也是目前个人电脑的主流,ARM 则是采用授权的方式发布,在移动设备崛起后,在手机、平板等各式嵌入式系统中广为使用。其他 ISA 在这种状况下可说是愈来愈少见了。

  然而,X86 和 ARM 的专利被少数几家把持住,厂商需要付出高额的授权费才能使用 ARM,X86 甚至不授权给予其他厂商使用。在物联网设备都需要内建微型电脑来运作下,为 ISA 授权金垫高的成本就造成了另一种阻碍。

  避免授权金突围,RISC-V 登场

  做为开源的 ISA,RISC-V 是由 UC Berkeley 所发展的,RISC-V 正试着挑战现行主流的指令集架构。藉由 RISC-V,UC Berkeley 正试着从头打造一个全新的生态系,并将其开放,让所有人都可以使用。但是,为何要重新建造一个全新的指令集架构?

  以开源的角度来说,软件的生态系比芯片的生态系完善。在软件世界中,任何一套商业软件大多有和其功能类似的开源版本,且功能不逊于商业版本。但是,至今却没有高能见度的开源 ISA 在市场中出现,如果有一套稳定且好用的开源 ISA 出现,或将打破现行被垄断的情形,避免授权所带来的开发成本,也可能改善现在持有 ISA 专利的厂商对授权的态度。

  简单易上手开发的优势

  除了授权的问题外,X86 和 ARM 的手册皆有上千多页,对工程师而言是相当大的负担,因为要设计一颗 CPU,工程师就要熟悉 ISA 中的所有规定,越熟悉才能设计出越好的 CPU。至于 RISC-V 则只需要约 100 页左右,大幅缩小工程师的负担。

  从官网上的文件可以知道,RISC-V 只有大约 100 个 Instructions,且不会再增加。如此便不需为了新增指令而增加新的电路,增加芯片的面积。此外,RISC-V 提供 16、32、64bits 等多种内存定址方式,让厂商有更多的选择。

  在软件支持方面,因为 RISC-V 是全新的指令集架构,因此现行的软件都要做修整方能配合使用。为了做后续的发展,他们已经为 RISC-V 开发出 GCC / glibc / GDB、LLVM / Clang、Linux、Yocto、Verification Suite 等软件。

  在硬件开发工具部分,他们设计出全新的硬件描述语言 Chisel,以 Scala 为语言核心,辅以硬件开发工具,可以将 Scala 所开发出的电路轻易地转换成 C++ 的电路模拟,或者 FPGA、ASIC 用的 Verilog Code,并进行合成和绕线,提升硬件设计的效率。

  实做产品足以挑战 ARM

  为了证明 RISC-V 的实际效能,UC Berkeley 甚至实际设计出一颗芯片,并将其制作出来。为了确保公平性,还特别选用和 ARM Cortex-A5 相同的台积电制程。从下图可以得知,采用 RISC-V 的 CPU 不但面积比较小,运算速度较快,而且还耗较少的电。足以证明 RISC-V 做为新进者,已经具有挑战 ARM 的潜力。

■ 利润不受制于人

购买ARM指令集授权的价格非常昂贵,据笔者了解仅仅ARM64指令集每5年的授权费就高达上千万美元乃至近亿美元。而恰恰是如此高昂的授权费致使由U.C. Berkeley等几个大学推出RISC-V指令集,Google、惠普、Oracle、西部数据等公司成立RISC-V基金会的原因——

RISC-V指令集是一个没有专利问题和没有历史包袱的全新指令集,并且以BSD许可证发布。任何公司都可以在自己的产品中免费使用,而修改也无需再开源。

购买ARM IP核授权,比如ARM的A53或A57,集成自己的SOC,这种做法虽然能依附于AA体系,有利于市场化运营,能赚快钱,但在利润方面也被外商控制。因为在购买IP要支付授权费,每生产一片芯片还要支付专利费。而且每个环节做什么,有多少利润,在AA体系中已经形成潜规则,国内IC设计公司依附于AA体系基本上沦为外商的马仔。这也是国内ARM阵营IC设计公司虽然营业收入不低,但利润普遍不高的原因之一。



IPB Image

(Source:RISC-V 官网)

IPB Image

RISC-V 演示板

  至此,可以了解 RISC-V 的基本生态圈已经建立起来。但是,距离正式商业性产品的发布还需要一段时间,将来会如何发展尚未明瞭。不过,从 RISC-V Rocket 的效能来看,要进入 IoT 的市场是相当容易的。此外,他们已经将设计且验证完的 CPU 程序码变成 open source,在官网中便可找到

引用
PULPino: open-source microcontroller based on a 32-bit RISC-V core

http://img0.tuicool.com/7ZjMBrE.png!web

Introduction

PULPino is an open-source microcontroller system, based on a small 32-bit RISC-V core developed at ETH Zurich. The core has an IPC close to 1, full support for the base integer instruction set (RV32I), compressed instructions (RV32C) and partial support for the multiplication instruction set extension (RV32M). It implements several ISA extensions such as: hardware loops, post-incrementing load and store instructions, ALU and MAC operations, which increase the efficiency of the core in low-power signal processing applications.

To allow embedded operating systems such as FreeRTOS to run, a subset of the privileged specification is supported. When the core is idle, the platform can be put into a low power mode, where only a simple event unit is active and everything else is clock-gated and consumes minimal power (leakage). A specialized event unit wakes up the core in case an event/interrupt arrives.

For communication with the outside world, PULPino contains a broad set of peripherals, including I2S, I2C, SPI and UART. The platform internal devices can be accessed from outside via JTAG and SPI which allows pre-loading RAMs with executable code. In standalone mode, the platform boots from an internal boot ROM and loads its program from an external SPI flash.

The PULPino platform is available for RTL simulation as well FPGA. PULPino has been taped-out as an ASIC in UMC 65nm in January 2016. It has full debug support on all targets. In addition we support extended profiling with source code annotated execution times through KCacheGrind in RTL simulations.

Requirements

PULPino has the following requirements

ModelSim in reasonably recent version (we tested it with versions >= 10.2c)
CMake >= 2.8.0, versions greater than 3.1.0 recommended due to support for ninja
riscv-toolchain, specifically you need riscv32-unknown-elf-gcc compiler and friends. There are two choices for this toolchain: Either using the official RISC-V toolchain supported by Berkeley or the custom RISC-V toolchain from ETH. The ETH version supports all the ISA extensions that were incorporated into the RI5CY core.
python2 >= 2.6
Editions

There are two PULPino editions available, one for OR1K based on the OR10N core and one for RISCV based on the RI5CY core. Only the RISC-V based version is currently open-source. The software included in this repository is compatible with both ISAs and automatically targets the correct ISA based on the compiler used.

The simulator (modelsim) must be explicitely told which edition you want to build. Use the environment variable PULP_CORE and set it to either OR10N or riscv. It defaults to riscv when not set.

Version Control

PULPino uses multiple git subrepositories

To clone those subrepositores and update them, use

./update-ips.py
This script will read the ips_lists.txt file and update to the versions specified in there. You can choose specific commits, tags or branches.

Documentation

There is a preliminary datasheet available that includes a block diagram and a memory map of PULPino. See docs/datasheet/ in this repository.

It is written in LaTeX and there is no pdf included in the repository. Simply type

make all
inside the folder to generate the pdf. Note that you need a working version of latex for this step.

Running simulations

The software is built using CMake. Create a build folder somewhere, e.g. in the sw folder

mkdir build
Copy the cmake-configure.{or1k/riscv}.{gcc/llvm}.sh bash script to the build folder. This script can be found in the sw subfolder of the git repository.

Modify the cmake-configure script to your needs and execute it inside the build folder. This will setup everything to perform simulations using ModelSim.

Inside the build folder, execute

make vcompile
to compile the RTL libraries using ModelSim. CMake automatically takes care of setting the PULP_CORE environment variable to the correct value based on the compiler you specified when configuring cmake.

To run a simulation in the modelsim GUI use

make helloworld.vsim
To run simulations in the modelsim console use

make helloworld.vsimc
This will output a summary at the end of the simulation. This is intended for batch processing of a large number of tests.

Replace helloworld with the test/application you want to run.

Using ninja instead of make

You can use ninja instead make to build software for PULPino, just replace all occurences of make with ninja. The same targets are supported on both make and ninja.

Interactive debug

To interactively debug software via gdb, you need the jtag bridge as well as a working version of gdb for the ISA you want to debug. The debug bridge depends on the jtag_dpi package that emulates a JTAG port and provides a TCP socket to which the jtag bridge can connect to.

Utilities

We additionally provide some utilitiy targets that are supposed to make development for PULPino easier.

For disassembling a program call

make helloworld.read
To regenerate the bootcode and copy it to the rtl folder use

make boot_code.install
FPGA

PULPino can be synthesized and run on a ZedBoard. Take a look at the fpga subfolder for more information.


代码
SiFive商业RISC-V芯片设计/IP授权/流片协作服务企业

SiFive was founded by the creators of the free and open RISC-V architecture as a reaction to the end of conventional transistor scaling and escalating chip design costs.

https://www.sifive.com

http://www.eefocus.com/mcu-dsp/372616



http://riscv.org
https://github.com/riscv?page=1
https://github.com/ucb-bar/rocket
https://github.com/ucb-bar

https://en.wikipedia.org/wiki/RISC-V

引用


http://rise.cse.iitm.ac.in/shakti.html

https://bitbucket.org/casl/shakti_public

PULPino:

https://github.com/pulp-platform/pulpino

For more information on PULPino and PULP see our websites:

http://pulp.ethz.ch and http://www-micrel.deis.unibo.it/pulp-project/

OpenSoC Fabric

The OpenSoC Fabric is an ongoing project to create a open source network-on-chip generator capable of creating a synthesizeable network for connecting processors, memory and I/O devices.

OpenSoC Fabic Status
2-D Mesh or Flattened Butterfly network of arbitrary size
Wormhole routing
Virtual Channels
Run through ASIC flow

http://www.opensocfabric.org/

https://github.com/LBL-CoDEx/OpenSoCFabric

OpenSoC

Open Source System-on-Chip IP, Development, and Tools

http://www.opensoc.community/

RISC-V网盘分流:http://pan.baidu.com/s/1mitAHfE

开源IP核网盘分流:http://pan.baidu.com/s/1kUYDWknL y5q0

本资源基于开源BSD协议发行。

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