http://www.verycd.com/groups/mcu Thu, 24 Dec 2009 21:18:22 +0000 zh-cn Thu, 24 Dec 2009 21:18:22 +0000 VeryCD.com webmaster@verycd.com (webmaster) http://blogs.law.harvard.edu/tech/rss 4 http://www.verycd.com/groups/mcu/420776.topic 有资源下载,点击查看) Intel 8080 CPU Verilog core



PROJECT: 8080 CPU

LANGUAGE: VERILOG

TARGET: Xilinx xc3s1000-4



OVERVIEW



This core was implemented as a first project in Verilog by an old schematic

design engineer. There were a few reasons for implementing an 8080 processor.

First, it was the first true general purpose processor available. Second, it

was, by nature, designed to be compact in instruction set and implementation.

Third, it has a rich set of software applications, including assemblers,

compilers and operating systems.



More often, A Z80 target is used in Verilog or VHDL, with the idea that the

Z80 is the superset of the 8080. However, the Z80 is significantly more

complex than the 8080. The 8080 can make a useful maintainence processor for

SOC systems, since it consumes a small amount of resources. The 8080 has a

significant body of support, since it was a primary 8 bit processor before

the Z80, and coding for the 8080 instruction set often continued even after

general Z80 use, because that was the universal subset of both processors.



My own experience with 8080 coding lasted perhaps a year, then I switched

to the Z80. Although he Z80 was a significantly more usable processor to

code for than a 8080, it made a mildly non-orthogonal instruction set much

more so. I have worked on several processors through the series, including

working on the design for the Z280, a Z80 16 bit replacement at Zilog

Corporation, so hopefully nobody can accuse me of bias against the Z80 :-)



The core presented is completely compatible with the original 8080 instruction

set, although the exact handling of the two undefined bits in the status (flags)

register have not been verified to be identical to the original. This only

matters for "trick" code that expects a value which is pop'ed into the PSW

to be preserved when subsequently pushed. This core preserves all bits,

including the undefined bits, which means such code would function correctly.

Also needing verification to the original are the illegal opcodes, which on

this core are treated as nops.



The pinout is decidedly not compatible with the original pinout. The original

8080 pinout was a multiplexed nightmare that was never really designed to be

directly used. Intel was attempting to save on pins, and much of the CPU status

was sent out on every cycle via the data pins. Intel subsequently came out with

"demultiplexor" chips to result in simple signals.



The cpu8080 signals are a simple unmultiplexed 16 bit address, and a

bidirectional, separate 8 bit data bus. The read and write for each of memory

and I/O spaces are all separately decoded. An interrupt request and acknowledge

is implemented sufficient to allow an external interrupt controller to be

connected. A readint signal is implemented that is true for the entire time that

an interrupt fetch is occuring. This allows simple implementation of full

vectoring mode.



There were two vectoring modes on the 8080. The most famous one was the use of

a single instruction byte that was forced onto the data lines during an

interrupt acknowledge cycle. This instruction could be any valid instruction,

but was most likely a restart, which gave 8 possible vector locations for the

interrupt.



It was not as well known, but the original 8080 could accept a full 2 or 3 byte

instruction via the interrupt acknowledge cycle. This was used by advanced

Intel interrupt controllers to place a full CALL instruction on the data lines,

and thus achieve full arbitrary address vectoring. I have included such an

advanced interrupt controller as an accessory to the cpu8080 core, also in

verilog.



IMPLEMENTATION



The 8080 is implemented with a standard finite state machine. At the next

positive edge after reset, the state, PC, all of the bus signals are reset to

false, and the interrupt enable is set. All of the registers, including the

stack, are left undefined at reset.



At the fetch instruction state, the current pc is placed on the address bus,

and a read instruction cycle occurs. In fetch2, the readmem signal is

deactivated, and the opcode is now on the data lines. We read it without

latching.



The instruction decode starts by splitting the instruction by the top two bits.

This breaks down as follows:



00 - General instructions, including carry control, rotates, double adds,

increment and decrement, and many types of loads.

01 - The "mov" instruction.

10 - Register or memory to accumulator operations.

11 - General instructions, including jumps and calls, interrupt enable and

disable, and I/O.



The move and accumulator operations are handled as one case. The others both

break down into a further case based on the lower 6 bits of the instruction.



Quite a few instructions are handled in a single case. For these instructions,

the only required finish is to set the next pc, then set the next state back

to fetch instruction.



The other class of instruction is those that require other bus read or write

transactions to complete. This includes instructions that read or write memory,

and those that have a byte or word parameter following.



To handle these, there are quite a few states I call "follow" states. When a

fetch2 state handler needs extra states to complete, it sets the next state to

one of these follow states, and that state will occur on the next positive

clock. The follow states can then chain further follow states, and so on,

until the entire instruction is complete.



To "talk" between states, several registers are employed as "mailboxes". For

example, the regd register tells the follow states where to put fetched data

meant for a register.



Many multistate instructions are handled completely with follow states. However,

a system exists for more complex instructions I call the "macro state

generator". This is just a ROM that holds a series of follow states to be

chained up to complete instructions. These are much like subroutines, and they

use special follow states that get the next state from the macro table, then

advance the macro state selector. The chain of follow states ends when either

a terminal state is in the table, a state that ends by selecting the fetch

instruction 1 as the next state, or because the macro table specifically

selects that as the next state.



The most commonly used macro states are the read and write states. It takes

four states to write, and two to read. An instruction can use a lot of them,

and do it repetitively. For example, the "xthl" instruction must perform two

byte reads, followed by two byte writes. The read and write routines use

general registers to keep the addresses they must read or write, and up to

two bytes of data to be read or written.



The only submodule in cpu8080 is the alu. It knows how to implement 8 kinds of

arithmetic operations, add, add with carry, subtract, subtract with borrow, and,

or, xor and compare. All of the 8080 flags are calculated within the alu. The

compare operation is actually a subtract that discards the result, and passes

the A operand out as the result.



To operate the ALU, the input operands and flags are placed on its input

registers, then the output result and flags are moved to the appropriate

registers. Each time this occurs, we give a full cycle for the alu to perform

this action.



Scott Moore ]]> Tue, 28 Oct 2008 11:19:02 +0000 vwing1 topic-420776@verycd.groups http://www.verycd.com/groups/mcu/327915.topic 有资源下载,点击查看) OpenSPARC 源代码

SPARC

Sun UltraSPARC II处理器

SPARC，全称为“可扩充处理器架构”（Scalable Processor ARChitecture），是RISC微处理器架构之一。它最早于1985年由升阳电脑所设计，也是SPARC国际公司的注册商标之一。这家公司于 1989年成立，其目的是向外界推广SPARC，以及为该架构进行符合性测试。此外该公司为了扩阔SPARC设计的生态系统，SPARC国际也把标准开放，并授权予多间生产商采用，包括德州仪器、Cypress半导体、富士通等。由于SPARC架构也对外完全开放，因此也出现了完全开放原始码的LEON 处理器，这款处理器以VHDL语言写成，并采用LGPL授权。

SPARC架构原设计给工作站使用，及后应用在升阳、富士通等制造的大型SMP服务器上。而升阳开发的Solaris操作系统也是为SPARC设计的系统之一，除Solaris外，NeXTSTEP、Linux、FreeBSD、OpenBSD及NetBSD系统也提供SPARC版本。

现时最新版本的SPARC为第8及第9版，在2005年12月，升阳方面宣布其UltraSPARC T1处理器将采用开放原始码方式。



开源CPU--OpenSparc T1简介 FPGA级别

2006年3月，Sun宣布开源化其多核心UltraSparc T1 CPU的处理器设计，采用的是GNU通用公共许可证(GNU GPL license)。之前Sun已经公开了"Hypervisor"API规范，允许各公司将Linux、BSD 及其他操作系统移植到UltraSparc T1平台。

Sun是业界首家将复杂的硬件设计使用GNU GPL许可进行发布的公司，而此举也将为UltraSparc T1处理器增加曝光度，并吸引开发人员为该平台开发软硬件解决方案。

该硬件设计的开源发布包括64-bit UltraSparc T1的Verilog硬件描述语言源代码，验证套装和模拟模型，ISA规范及Solaris 10 OS虚拟镜像。T1处理器的代号为“Niagara”，于去年发布并应用于Sun的T1000/T2000服务器中。 Sun目前推出了4、6、8核心的CPU版本，且每核心最多支持4线程，即总共最多32线程。T1基于Sparc V9架构，每核心集成16KB指令缓存和8KB主数据缓存，整个处理器共享3MB L2缓存。“OpenSparc T1”芯片设计，验证套装，架构和性能模型工具已经发布在http://www.opensparc.net网站。Sun还发布了“Cool Tools”，其中包括优化多线程CPU性能的各种程序以及CMT编程及描绘工具。
OpenSparc T1处理器的主要特征包括：
8个Sparc V9处理核心，每核心4线程，共计32线程
每处理核心16KB一级指令缓存，共128KB；

每处理核心8KB一级数据缓存，共64KB；

3MB二级缓存，4-way bank，12向关联，各核心共享；

4个DDR2内存控制器，每通道位宽144bit，总带宽峰值25GB/s；

IEEE754兼容浮点单元(FPU)，各核心共享；

J-Bus输入输出接口，峰值带宽2.56GB/s，128bit多元地址/数据复用总线。



UltraSPARC T1



Sun UltraSPARC T2解析



新一代的UltraSPARC T2处理器带有8个核心，可以同时处理64个线程。T2的产品代号Niagra 2，不仅将应用在SUN自己的服务器上，还可能放在机顶盒、路由器等设备中。目前处理器由TI负责制造，采用SoC设计，带有2个以太网接口，1个 PCIe ×8接口和4个双通道FBDIMM内存控制器，整个处理器带有5.03亿个晶体管，核心大小342平方毫米，目前共推出1.2GHz与1.4GHz两种频率，在1.4GHz主频的电压为1.1伏，工作频率上功耗85W。




UltraSPARC T2设计蓝图

65纳米技术更节能

　　SUN已经成功将90纳米的制作工艺成功转制成65纳米工艺，这样意味着在同样面积的芯片上可以放入更多的模块。此外，T2还使用了其具有革命性的酷线程(CoolThreads?)芯片多线程技术(CMT)扩展到每线程功耗低于2瓦的UltraSPARC T2处理器。换句话说，拥有这项技术后，SUN的产品功耗将是竞争对手的十分之一或三十分之一。因此我们将看到业界功耗最低、8个内核、64个线程、4倍的吞吐量及网络和安全的功能性于一身的产品。


芯片特点
处理器 八核心 工作主频在900MHz – 1.4GHz
支持64线程
支持64 FB-DIMMs, 4个内存控制器
内存带宽 60+GB/S
功耗 标准95W或最高123W
其他特点 8个浮点运算单元(FPUs)
双10Gbit以太网接口和PCI-E支持
4MB二级缓存 (8 banks)



每核心1个安全协处理器
核心特点
核心特征 大小：12 mm2
8线程
2条指令管线 + 1个浮点计算 + 1个密码加速单元
8KB 数据缓存+ 16KB 指令缓存
其他应用
其他应用 单插槽的机架或刀片服务器
WiMAX 无线
3G/4G
网络基础构架


性能翻倍，新一代架构有突破

　　UltraSPARC T2处理器将单一芯片上集成的系统功能提升到空前水平，在性能方面也是T1的两倍。这首先要得益于它较高的吞吐量处理器能力，在 SPECint_rate2006和SPECfp_rate2006的测试中，这两项成绩分别是78.3 est和62.3 est，这主要得益于该处理器的8核和每核8线程的设计特色。在网络连接方面，该处理器支持两个可虚拟化的多线程的每秒10千兆比特的以太网端口，也就是万兆以太网接口，并具有内建的包分类功能。在安全方面，8个密码加速单元，一共有10个独立的功能，可满足不断增长的安全需求，包括由NSA批准的算法，在性能上也没有任何损失。

　除此之外，在计算方面8个浮点单元，SUN将CMT的技术优势扩展到了高性能计算领域，适用于各类科学应用，创立了单芯片 SPECfp_rate2006世界记录和单芯片，有8条通道的输入输出接口可以满足行业标准PCI Express I/O高速应用，如流媒体、数据库读/写，以及数据备份等。4个内存控制器，提供了每秒50千兆字节以上的内存访存速度。

以下表格中公布的是UltraSPARC T2单处理器的性能测试结果：

SPECint_rate2006 SPECfp_rate2006
1.4GHz Sun UltraSPARC T2 148％ 134％
4.7GHz IBM POWER 6 115％ 125％
2.66GHz Intel X5355 100％ 100％

开源让更多用户受益

　　UltraSparc T2也将和UltraSparc T1一样采用开放原始码授权，到目前为止，OpenSPARC T1源码的下载已经超过5,500次。现在Sun正准备将UltraSPARC T2的源码在www.opensparc.net上向OpenSPARC社团发布。并且提供了程序员参考手册、微架构技术规范、OpenSPARC T2β版评估项目等一系列措施，其中程序员参考手册里提供了软件端口、操作系统端口，以及加快OpenSPARC T2项目进展的应用工具。微架构技术规范里提供了对OpenSPARC T2硬件模块特性和功能的详细描述。OpenSPARC T2β版评估项目为一定数量的硬件设计人员和工具开发人员提供早期试用版，让他们开始使用具有片上系统功能性的最新CMT技术。该项目将促进 OpenSPARC T2社团的发展，加快调试过程，以获得性能更佳的OpenSPARC T2的第一个版本，配合具有海量线程特性的Solaris操作系统使高线程处理器UltraSPARC T2的技术优势得到充分发挥，拥有开放的、低成本的虚拟化功能。 ]]> Tue, 19 Aug 2008 17:48:00 +0000 vwing1 topic-327915@verycd.groups